caching controller造句

• The backup cache controller was located on the VC chip.
• It is connected to the cache controller by a 128-bit data path.
• The MMU die contains the memory management unit, cache controller and the external interfaces.
• The 82497 Cache Controller implements the MESI write-back protocol for full multiprocessing support.
• All cache controllers monitor the bus.
• The Mariah CPU, FPU and cache controller were designated DC595, DC596 and DC597 respectively.
• This was followed in 1989 by the A38202 cache controller, also for 80386-based systems.
• Austek produced a number of digital signal processing chips, but their most successful products were cache controllers.
• Instead, the processor has an on-chip cache controller which controls separate external data and instruction caches.
• Improvements were the addition of an on-chip secondary cache controller that supported up to 2 MB of cache.
• In early designs a " cache miss " would force the cache controller to stall the processor and wait.
• As the R4600 chip itself has no L2 cache controller, an external controller is used to add 512K of L2 cache.
• The B-cache is controlled by on-die external interface logic, unlike the 21064, which required an external cache controller.
• In addition, there is a 24 MB shared L3 cache implemented in eDRAM and controlled by two on-chip L3 cache controllers.
• In addition, there is a 48 MB shared L3 cache implemented in eDRAM and controlled by two on-chip L3 cache controllers.
• The secondary cache controller was not integrated on the MC88110, but was located on a separate device, the MC88410, to reduce cost.
• The leftover tag bit is instead used to store the cache line dirty bit, and all 16 Kbits in the cache controller are used for valid bits.
• The R5000 had an integrated L2 cache controller that supported capacities of 512 KB, 1 MB and 2 MB . The L2 cache shares the SysAD bus with the external interface.
• In 1987 it released the A38152, the world's first single-chip cache controller operating at 20 MHz and to enhance the performance of 80386-based computer systems.
• Enhancements over Rigel included a 4 kB first-level cache and 32-bit physical memory addressing in the Mariah CPU, and write-back caching implemented in the cache controller chip.